LTC1592 [Linear Systems]
12-/14-/16-Bit SoftSpan DACs with Programmable Output Range; 12位/ 14位/ 16位的SoftSpan数模转换器，具有可编程输出范围
| 型号： | LTC1592 |
| 厂家： | 
Linear Systems |
| 描述： | 12-/14-/16-Bit SoftSpan DACs with Programmable Output Range |
| 文件： | 总16页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1588/LTC1589/LTC1592
12-/14-/16-Bit SoftSpan DACs
with Programmable Output Range
U
FEATURES
DESCRIPTIO
■
Six Programmable Output Ranges
TheLTC®1588/LTC1589/LTC1592areserialinput12-/14-
/16-bit multiplying current output DACs that operates
Unipolar Mode: 0V to 5V, 0V to 10V
Bipolar Mode: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
1LSB Max DNL and INL Over the Industrial
Temperature Range
from a single 5V supply. These SoftSpanTM DACs can be
software-programmed for either unipolar or bipolar mode
through a 3-wire SPI interface. In either mode, the voltage
output range can also be software-programmed. Two
output ranges in unipolar mode and four output ranges in
bipolar mode are available.
■
■
■
■
■
Glitch Impulse < 2nV-s
16-Lead SSOP Package
Power-On Reset to 0V
Asynchronous Clear to 0V for All Ranges
INL and DNL are accurate to 1LSB over the industrial
temperature range in both unipolar and bipolar modes.
True 16-bit 4-quadrant multiplication is achieved with
on-chip four quadrant multiplication resistors. The
LTC1588/LTC1589/LTC1592 are available in a 16-lead
SSOP package.
U
APPLICATIO S
■
Process Control and Industrial Automation
■
Precision Instrumentation
■
Direct Digital Waveform Generation
These devices include an internal deglitcher circuit that
reduces the glitch impulse to less than 2nV-s (typ).
■
Software-Controlled Gain Adjustment
■
Automatic Test Equipment
TheasynchronousclearpinresetstheLTC1588/LTC1589/
LTC1592 to 0V in unipolar or bipolar mode.
, LTC and LT are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Programmable Output Range 16-Bit SoftSpan DAC
V
REF
5V
LTC1592 Integral Nonlinearity
5
6
+
1.0
7
1/2 LT®1469
0.8
0.6
–
C2
150pF
0.4
0.2
2
1
16 15
R2
3
4
0
R1
R
R
REF
R
COM
FB
OFS
C1
–0.2
–0.4
–0.6
–0.8
–1.0
R1
R2
15pF
0.1µF
9
15V
8
V
5V
CC
0.1µF
I
I
–
OUT1
OUT2
5
2
3
1
14
13
12
11
10
16-BIT DAC WITH SPAN ADJUST
LTC1592
V
OUT
1/2 LT1469
+
CLR
CS/LD
SCK
SDI
6
7
8
0
32768
DIGITAL INPUT CODE
49152
16384
65535
4
AGND
GND
1588992 TA02
–15V
0.1µF
SDO
1588992 TA01
1588992fa
1
LTC1588/LTC1589/LTC1592
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC to AGND, GND ......................................–0.3V to 7V
AGND to GND .............................. –0.3V to (VCC + 0.3V)
GND to AGND .............................. –0.3V to (VCC + 0.3V)
ORDER PART
NUMBER
TOP VIEW
R
1
2
3
4
5
6
7
8
16 R2
COM
R1
LTC1588CG
LTC1588IG
LTC1589CG
LTC1589IG
LTC1592ACG
LTC1592AIG
LTC1592BCG
LTC1592BIG
15 REF
14 CLR
13 CS/LD
12 SCK
11 SDI
10 SDO
R
COM to AGND, GND ................................ –0.3V to 12V
R
OFS
REF to AGND, GND ................................................ ±15V
ROFS, RFB, R1, R2 to AGND, GND .......................... ±15V
Digital Inputs to AGND, GND ....... –0.3V to (VCC + 0.3V)
IOUT1, IOUT2 to AGND, GND.......... –0.3V to (VCC + 0.3V)
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range
LTC1588C/LTC1589C/LTC1592C ........... 0°C to 70°C
LTC1588I/LTC1589I/LTC1592I........... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
R
FB
I
I
OUT1
OUT2
AGND
GND
9
V
CC
G PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 125°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = TMIN to TMAX
,
VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V.
LTC1588
LTC1589
LTC1592B
LTC1592A
SYMBOL PARAMETER
Accuracy
CONDITIONS
TEMPERATURE
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Resolution
●
12
14
16
16
Bits
INL
DNL
GE
Integral
Nonlinearity
(Notes 2, 3)
T = 25°C
±1
±1
±1
±1
±2
±2
±0.3 ±1
±0.4 ±1
LSB
LSB
A
T
MIN
to T
●
●
MAX
Differential
Nonlinearity
Guaranteed
Monotonic (Note 3)
T
MIN
to T
±1
±1
±1
±0.2 ±1
LSB
MAX
Gain Error
All Output Ranges
(Note 3)
T = 25°C
–0.20 ±3
–0.22 ±3
–1.0 ±4
–1.3 ±6
–3 ±16
–4 ±24
–2 ±16
–3 ±16
LSB
LSB
A
T
MIN
to T
●
MAX
BZE
Bipolar Zero Error All Bipolar Ranges
(Note 3)
T = 25°C
±1
±1
±2.5
±4.0
±10
±16
±5
±8
LSB
LSB
A
T
MIN
to T
●
●
MAX
Gain Temperature ∆Gain/∆Temperature
3
3
3
1
3
ppm/°C
Coefficient
(Note 4)
I
I
Leakage
(Note 5)
T = 25°C
±5
±15
±5
±15
±5
±15
±5
±15
nA
nA
LKG
OUT1
A
Current
T
MIN
to T
●
●
MAX
PSRR
Power Supply
Rejection
V
CC
= 5V ±10%
±0.01±0.15
±0.05 ±0.5
±2
±0.2 ±2
LSB/V
1588992fa
2
LTC1588/LTC1589/LTC1592
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V.
SYMBOL PARAMETER
Reference Input
CONDITIONS
MIN
TYP
MAX
UNITS
R
DAC Input Resistance (Unipolar)
(Note 6)
●
●
5
7
10
20
kΩ
kΩ
REF
R1, R2 R1, R2 Resistance
(Notes 6, 11)
10
14
R
R
Offset Resistance (Bipolar)
±5V, ±10V, ±2.5V Ranges
–2.5V to 7.5V Range
●
●
10
20
14
28
20
40
kΩ
kΩ
OFS
Feedback Resistance (Unipolar)
Feedback Resistance (Bipolar)
5V Range
10V Range
●
●
5
10
7
14
10
20
kΩ
kΩ
FB
±5V and –2.5V to 7.5V Ranges
±10V Range
±2.5V Range
●
●
●
10
20
5
14
28
7
20
40
10
kΩ
kΩ
kΩ
Analog Outputs (Note 4)
Output Capacitance (I
C
)
OUT1
DAC Load All 1s
DAC Load All 0s
160
100
pF
pF
OUT
AC Performance (Note 4)
Settling Time
5V Range, 0V to 5V Step with LT1468 (Note 7)
(Note 10)
2
2
µs
Midscale Glitch Impulse
nV-s
Multiplying Feedthrough Error
Total Harmonic Distortion
Output Noise Voltage Density
V
= ±10V, 10kHz Sine Wave
1
mV
P-P
REF
THD
(Note 8) Multiplying
(Note 9) At I
–108
11
dB
nV/√Hz
OUT1
Digital Inputs
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
●
●
●
●
2.4
V
V
IH
IL
0.8
±1
8
I
µA
pF
IN
C
Digital Input Capacitance
V
= 0V (Note 4)
IN
IN
Digital Outputs
V
V
Digital Output High Voltage
Digital Output Low Voltage
I
I
= 200µA
●
●
4
V
V
OH
OL
OH
OL
= 1.6mA
0.4
Timing Characteristics
t
t
t
t
t
t
t
t
t
t
t
Serial Input Valid to SCK Setup Time
Serial Input Valid to SCK Hold Time
SCK Pulse Width High
●
●
●
●
●
●
●
●
●
●
●
●
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
35
35
360
35
0
3
SCK Pulse Width Low
4
CS/LD Pulse High Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
5
6
7
SCK to SDO Propagation Delay
SCK Low to CS/LD Low
C
= 50pF
LOAD
20
35
100
35
180
8
9
Clear Pulse Low Width
10
11
CS/LD High to SCK Positive Edge
SCK Frequency
Non-Daisy Chain (Note 12)
Daisy Chain (Note 13)
14.2
4.1
MHz
MHz
1588992fa
3
LTC1588/LTC1589/LTC1592
The ● denotes specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are TA = TMIN to TMAX, VCC = 5V, VREF = 5V, IOUT2 = AGND = GND = 0V.
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
●
●
4.5
5
5.5
10
V
CC
I
Supply Current, V
Digital Inputs = 0V or V
CC
µA
CC
CC
Note 9: Calculation from e = √4kTRB where: k = Boltzmann constant
(1.38E-23 J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth
(Hz).
Note 10: Midscale transition code: 32767 to 32768 for the LTC1592, 8191
to 8192 for the LTC1589, 2047 to 2048 for the LTC1588.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale
(LTC1592). ±1LSB = ±0.006% of full scale = ±61.2ppm of full scale
(LTC1589). ±1LSB = 0.024% of full scale = ±244.8ppm of full scale
(LTC1588).
n
Note 11: R1 and R2 are measured between R1 and R , R2 and R
COM
.
COM
Note 3: Using internal feedback resistor.
Note 12: If a continuous clock is used with data changing on the rising
edge of SCK, setup and hold time (t , t ) will limit the maximum clock
Note 4: Guaranteed by design, not subject to test.
1
2
frequency. If data changes on the falling edge of SCK then the setup time
will limit the maximum clock frequency to 8MHz (continuous 50% duty
cycle clock).
Note 5: I
with DAC register loaded to all 0s.
OUT1
Note 6: Typical temperature coefficient is 100ppm/°C.
Note 7: To 0.0015% for a full-scale change, measured from the falling
edge of LD for the LTC1592 only.
Note 8: REF = 6V
Note 13: SDO propagation delay and SDI setup time (t , t ) limit the
8
1
maximum clock frequency for daisy chaining.
at 1kHz. DAC register loaded with all 1s. Output
RMS
amplifier = LT1468.
U W
(LTC1588/LTC1589/LTC1592)
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Input Voltage
Logic Threshold vs Supply Voltage
Midscale Glitch Impulse
3.0
2.5
2.0
1.5
1.0
0.5
0
5
4
3
2
1
0
40
30
20
10
V
CC
= 5V
USING AN LT1468
ALL DIGITAL INPUTS
TIED TOGETHER
C
V
= 30pF
FEEDBACK
REF
= 10V
0
1nV-s TYPICAL
–10
–20
–30
–40
0
2
3
4
5
6
7
1
0
1
2
3
4
5
0.2
0.4
TIME (µs)
0.8
0
1.0
0.6
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
1588992 G10
1588992 G09
1588992 G03
1588992fa
4
LTC1588/LTC1589/LTC1592
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC1588)
Integral Nonlinearity
Differential Nonlinearity
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
800
1600
2400
3200
4095
0
800
1600
2400
3200
4095
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1588992 G11
1588992 G12
(LTC1589)
Integral Nonlinearity
Differential Nonlinearity
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4112
8224
12336
16383
0
4112
8224
12336
16383
DIGITAL INPUT CODE
DIGITAL INPUT CODE
1588992 G13
1588992 G14
(LTC1592)
Integral Nonlinearity (INL)
Integral Nonlinearity
vs Reference Voltage
in Unipolar Mode
Differential Nonlinearity (DNL)
1.0
1.0
1.0
0.8
0.8
0.6
0.8
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32768
49152
0
32768
49152
16384
65535
–10 –8 –6 –4 –2
0
2
4
6
8
10
16384
65535
DIGITAL INPUT CODE
DIGITAL INPUT CODE
REFERENCE VOLTAGE (V)
1588992 G02
1588992 G01
1588992 G05
1588992fa
5
LTC1588/LTC1589/LTC1592
U W
TYPICAL PERFOR A CE CHARACTERISTICS (LTC1592)
Differential Nonlinearity
vs Reference Voltage
in Unipolar Mode
Integral Nonlinearity
vs Reference Voltage
in Bipolar Mode
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–10 –8 –6 –4 –2
0
2
4
6
8
10
–10 –8 –6 –4 –2
0
2
4
6
8
10
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
1588992 G06
1588992 G07
Differential Nonlinearity
vs Reference Voltage
in Bipolar Mode
Full-Scale Settling Waveform
1.0
0.8
0.6
LD PULSE
5V/DIV
0.4
0.2
GATED
SETTLING
WAVEFORM
500µV/DIV
0
–0.2
–0.4
–0.6
–0.8
–1.0
500ns/DIV
1592 G04
USING LT1468 OP AMP
CFEEDBACK = 20pF
0V TO 10V STEP
–10 –8 –6 –4 –2
0
2
4
6
8
10
REFERENCE VOLTAGE (V)
1588992 G08
U
U
U
PI FU CTIO S
RCOM (Pin 1): Center Tap Point of the Two Bipolar Resis-
tors R1 and R2. Normally tied to the inverting input of an
external amplifier. When these resistors are not used,
connect this pin to ground. The absolute maximum volt-
age range on this pin is –0.3V to 12V.
ROFS (Pin3):BipolarOffsetNetwork. Thispinprovidesthe
offset of the output voltage range for bipolar modes.
Accepts up to ±15V. Normally tied to R1 and the reference
input voltage VREF (5V). Alternatively, this pin may be
driven from a different voltage than VREF
.
R1 (Pin 2): Bipolar Resistor R1. The main reference input
VREF, typically 5V. Accepts up to ±15V. Normally tied to
ROFS (Pin 3) and the reference input voltage VREF (5V).
When not used connect this pin to ground.
RFB (Pin4):FeedbackNetwork.Normallytiedtotheoutput
of the current to voltage converter op amp. Range limited
to ±15V.
1588992fa
6
LTC1588/LTC1589/LTC1592
U
U
U
PI FU CTIO S
IOUT1 (Pin 5): True DAC Current Output. Tied to the
inverting input of the current-to-voltage op amp.
SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
isshiftedintotheinputshiftregisteronrisingedgeofSCK.
IOUT2 (Pin 6): Complement of DAC Current Output. Nor-
CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCKisenabledforshiftingdataintotheinputshiftregister.
WhenCS/LDispulledhigh,SCKisdisabledandthecontrol
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).
mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system’s analog
ground plane.
GND (Pin 8): Ground. Tie to the system’s analog ground
plane.
CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.
VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V.
Requires a 0.1µF bypass capacitor to ground.
REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to ±15V.
SDO(Pin10): SerialDataOutput. Dataatthispinisshifted
out on the rising edge of SCK.
R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
referenceinputREF(Pin15)andtheoutputoftheinverting
amplifier tied to RCOM (Pin 1).
SDI (Pin 11): Serial Data Input.
U
U
FU CTIO TABLE
Table 1
Internal Register Status
SREG
DATA WORD
Dn IN INPUT
BUF1
BUF2
DAC
BUFFER
(DAC OUTPUT)
No Change
Dn
COMMAND
OPERATION
EACH COMMAND IS EXECUTED
ON THE RISING EDGE OF CS/LD
DAC
OUTPUT
RANGE
No Change
No Change
No Change
INPUT
C3 C2 C1 C0
SHIFT REGISTER BUFFER
Dn
X
Dn
Dn
Dn
Dn
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Copy Data Word Dn in SReg to Buf1
Copy the Data in Buf1 to Buf2
Copy Data Word Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to ±5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to ±10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to ±2.5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
5V
10V
±5V
±10V
±2.5V
–2.5V to 7.5V
X
No Change No Change
No Change
No Operation
Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.
1588992fa
7
LTC1588/LTC1589/LTC1592
W
BLOCK DIAGRA
SDI
BUF1
BUF2
SREG
12-/14-/16-BIT
DATA WORD
BUFFER 12/14/16 BUFFER 12/14/16
BITS BITS
12-/14-/16-BIT DAC
SPAN ADJUST
Dn
SCK
24-BIT
SHIFT
REGISTER
4 BIT
COMMAND
WORD
DECODER
1588992 BD
8-BIT
SHIFT
REGISTER
SDO
CS/LD
W U
W
TI I G DIAGRA
t
1
t
t
t
t
4
6
2
3
1
2
23
24
SCK
t
t
11
9
SDI
t
t
7
5
CS/LD
SDO
t
8
1588992 TD
1588992fa
8
LTC1588/LTC1589/LTC1592
U
OPERATIO
INPUT WORD (LTC1588)
COMMAND
DON’T CARE
DATA (12 BITS + 4 DON’T-CARE BITS)
X
X
X
D6
D5 D4 D3 D2 D1
D0
X
X
X
X
X
C3
C1
X
D11 D10 D9 D8
MSB
D7
C2
C0
1588992 TD4
LSB
INPUT WORD (LTC1589)
COMMAND
DON’T CARE
DATA (14 BITS + 2 DON’T-CARE BITS)
X
X
X
X
X
D12
D6
D0
X
C3
C1
X
D13
D11 D10 D9 D8
D5 D4 D3 D2 D1
D7
C2
C0
C0
1588992 TD3
MSB
LSB
INPUT WORD (LTC1592)
COMMAND
DON’T CARE
DATA (16 BITS)
D6
D5 D4 D3 D2 D1
X
D12
D0
C3
C1
X
D15 D14 D13
MSB
D11 D10 D9 D8
D7
C2
LSB
1588992 TD2
Serial Interface
clocked to all ICs, then the CS/LD signal is pulled high to
update all of them simultaneously.
When the CS/LD is brought to a logic low, the data on the
SDIinputisloadedintotheshiftregisterontherisingedge
of the clock. A 4-bit command word (C3 C2 C1 C0),
followed by four “don’t care” bits and 16 data bits
(MSB-first)istheminimumloadingsequencerequiredfor
the LTC1588/LTC1589/LTC1592. When the CS/LD is
brought to a logic high, the clock is disabled internally and
the command word is executed.
Power-On Reset and Clear
When the power supply is first turned on, the LTC1588/
LTC1589/LTC1592 will power up in 5V unipolar mode (C3
C2 C1 C0 = 1000). All the internal registers are set to zeros
and the DAC is set to zero code.
The LTC1588/LTC1589/LTC1592 must first be pro-
grammed in either unipolar or bipolar mode. There are six
operating modes available and can be software-pro-
grammed by the command word. When a CLR signal is
brought to low, it clears all internal registers to zero. The
DAC output voltage goes to zero volts. If an update DAC
command (C3 C2 C1 C0 = 0001) is issued immediately
after the CLR signal, the DAC output remains at zero volts.
If no daisy-chaining is required, the input stream can be
24-bitwideasshowninFigure1a.Thefirstfourbitsarethe
command word, followed by four “don’t care” bits, then a
16-bit data word. The last four bits (LSBs) of this 16-bit
data word are don’t cares for the LTC1588. For the
LTC1589, the last 2 bits of the 16-bit data word are don’t
cares.
IfaCLRsignalisgivenwithina100nsintervalimmediately
after CS/LD goes high, the user should reload the output
range.
If daisy-chaining is required or the input needs to be
writtenintwo16-bitwidesegments, thentheinputstream
must be 32-bit wide and the first 8 bits loaded are “don’t
care” bits. The remaining bits work the same as a 24-bit
stream which is described in the previous paragraph. The
outputoftheinternal32-bitshiftregisterisavailableonthe
SDO pin 32 clock cycles later.
Output Range Programming
There are two output ranges available in unipolar mode
and four output ranges available in bipolar mode. See
Function Table for details. All output ranges are with re-
specttoa5Vreferenceinput.WhenchangingtheLTC1588/
LTC1589/LTC1592 to a new mode, the command word
and data are given at the same time (24 or 32 bit). When
Multiple LTC1588/LTC1589/LTC1592s may be daisy-
chained together by connecting the SDOpin to the SDI pin
of the next IC. The clock and CS/LD signals should remain
common to all ICs in the daisy-chain. The serial data is
1588992fa
9
LTC1588/LTC1589/LTC1592
U
OPERATIO
1588992fa
10
LTC1588/LTC1589/LTC1592
U
OPERATIO
CS/LD goes high, the mode changes and the DAC output
3. Using a 32-bit load sequence, load the bipolar range of
±10V with the DAC output voltage at 5V initially. Then
change the DAC output to –5V:
goes to a value corresponding to the data code.
Examples using the LTC1592:
a) CS/LD
1. Using a 24-bit loading sequence, load the unipolar
range of 0V to 10V with the DAC output at zero volt:
b) ClockSDI=XXXXXXXX1011XXXX110000000000
0000
a) CS/LD
c) CS/LD ; then VOUT = 5V on the ±10V range
b) Clock SDI = 1001 XXXX 0000 0000 0000 0000
c) CS/LD ; then VOUT = 0V
Next, the bipolar range of ±10V is retained and the DAC
output voltage is changed to VOUT = –5V:
2. Using a 24-bit loading sequence, load the bipolar range
a) CS/LD
of ±5V and the DAC output at zero volt:
b) ClockSDI=XXXXXXXX0010XXXX010000000000
0000
a) CS/LD
b) Clock SDI = 1010 XXXX 1000 0000 0000 0000
c) CS/LD ; then VOUT = 0V on the ±5V range
c) CS/LD ; then VOUT = –5V on the ±10V range
W U U
U
APPLICATIO S I FOR ATIO
Op Amp Selection
Table 4 contains a partial list of LTC precision op amps
recommended for use with the LTC1592. The easy-to-use
designequationssimplifytheselectionofopampstomeet
the system’s specified error budget. Select the amplifier
from Table 4 and insert the specified op amp parameters
in Table 3. Add up all the errors for each category to
determine the effect the op amp has on the accuracy of the
LTC1592.Arithmeticsummationgivesan(unlikely)worst-
case effect. A root-sum-square (RMS) summation pro-
duces a more realistic estimate.
Because of the extremely high accuracy of the 16-bit
LTC1592, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 2 and 3 contain equations for evaluating the effects
of op amp parameters on the LTC1592’s accuracy when
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipo-
largainerror. Tables2and3canalsobeusedtodetermine
the effects of op amp parameters on the LTC1589 and the
LTC1588. However, the results obtained from Tables 2
and 3 are in 16-bit LSBs. Divide these results by 4
(LTC1589) and 16 (LTC1588) to obtain the correct LSB
sizing.
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For the
LTC1592,a250µVopampoffsetwillcauseabout0.65LSB
INLdegradationand0.15LSBDNLdegradationwitha10V
full-scale range (20V range in bipolar). For the LTC1592
programmed in a unipolar mode, the same 250µV op amp
offset will cause a 3.3LSB zero-scale error and a 3.3LSB
gain error with a 10V full-scale range.
1588992fa
11
LTC1588/LTC1589/LTC1592
W U U
U
APPLICATIO S I FOR ATIO
While not directly addressed by the simple equations in
Tables 2 and 3, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to find the worst-case VOS and IB
over temperature. Then, plug these numbers in the VOS
and IB equations from Table 3 and calculate the tempera-
ture induced effects.
Advances Ensure 16-Bit DAC Settling Time,” offers a thor-
ough discussion of 16-bit DAC settling time and op amp
selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifier
for use with the LTC1592 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC1592
is directly affected by the voltage reference; thus, any
voltagereferenceerrorwillappearasaDACoutputvoltage
error.
For applications where fast settling time is important, Appli-
cation Note 74, entitled “Component and Measurement
Table 2. Variables for Each Output Range That Adjust the
Equations in Table 3
OUTPUT RANGE
A1
1.1
2.2
2
A2
2
A3
A4
A5
1
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit applica-
tions: output voltage initial tolerance, output voltage tem-
perature coefficient and output voltage noise.
5V
10V
3
1.5
1.5
2.5
1
±5V
2
1.2
1.2
1.6
1
1
1
±10V
4
4
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
±2.5V
1
1
1
–2.5V to 7.5V
1.9
3
0.5
1.5
Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges
UNIPOLAR
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
BIPOLAR GAIN
ERROR (LSB)
OP AMP
INL (LSB)
5V
DNL (LSB)
5V
OFFSET (LSB)
5V
REF
5V
REF
5V
REF
5V
REF
V
(mV)
V
• 2.4 •
V
• 0.6 •
V
• 13.2 •
A3 • V
OS1
• 19.8 •
V
• 13.2 •
V
• 13.2 •
OS1
(V
(V
(V
(V
(V
(V
)
)
)
)
)
)
)
OS1
OS1
OS1
OS1
OS1
REF
REF
5V
REF
5V
REF
5V
REF
5V
REF
5V
(V
5V
REF
I
(nA)
I
• 0.0003 •
I
• 0.00008 •
I
• 0.13 •
I
• 0.01 •
0
I
• 0.0018 •
I
• 0.0018 •
(V
(V
B1
B1
B1
B1
B1
B1
B1
)
(V
(V
(V
)
)
)
)
REF
( 16.5k)
1.5k
VOL1
131k
VOL1
131k
VOL1
A
(V/V)
(mV)
A1 •
A2 •
0
0
0
0
A5 •
A5 •
VOL1
)
A
(A
0
)
)
(A
(A
VOL1
5V
5V
5V
REF
5V
REF
V
0
0
0
A4 • V
• 13.1 •
V
• 26.2 •
• 0.1 •
V
• 26.2 •
OS2
OS2
OS2
OS2
(V
)
(V
(V
(
))
))
)
REF
REF
5V
5V
I
(mV)
0
0
A4 • I • 0.05 •
I
I
B2
• 0.1 •
131k
B2
B2
B2
(
(V
REF
)
)
(V
(V
REF
66k
131k
(A
A
(V/V)
A4 •
VOL2
)
(A
)
)
(A
VOL2
VOL2
VOL2
Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1588/LTC1589/LTC1592,
with Relevant Specifications
AMPLIFIER SPECIFICATIONS
VOLTAGE
NOISE
nV/√Hz
CURRENT
NOISE
pA/√Hz
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
t
POWER
DISSIPATION
mW
SETTLING
V
µV
I
nA
A
OL
V/mV
with LTC1592
OS
B
AMPLIFIER
LT1001
µs
25
2
800
10
14
14
2.7
5
0.12
0.008
0.008
0.3
0.25
0.2
0.16
4.5
22
0.8
0.7
120
120
115
19
46
11
LT1097
50
0.35
0.25
20
1000
1500
4000
5000
2000
LT1112 (Dual)
LT1124 (Dual)
LT1468
60
0.75
12.5
90
10.5/Op Amp
69/Op Amp
117
70
75
10
0.6
2.5
2.5
LT1469 (Dual)
125
10
5
0.6
22
90
123/Op Amp
1588992fa
12
LTC1588/LTC1589/LTC1592
U
W U U
APPLICATIO S I FOR ATIO
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the refer-
ence; however, a calibration sequence that corrects for
system zero- and full-scale error is always recommended.
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. IOUT2 must be tied
to the star ground with as low a resistance as possible.
A reference’s output voltage temperature coefficient af-
fects not only the full-scale error, but can also affect the
circuit’s INL and DNL performance. If a reference is
chosen with a loose output voltage temperature coeffi-
cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient condi-
tions. Minimizing the error due to reference temperature
coefficient can be achieved by choosing a precision
reference with a low output voltage temperature coeffi-
cient and/or tightly controlling the ambient temperature
of the circuit to minimize temperature gradients.
WhenitisnotpossibletolocatestargroundclosetoIOUT2
,
a low resistance trace should be used to route this pin to
star ground. This minimizes the voltage drop from this pin
to ground caused by the code dependent current flowing
to ground. When the resistance of this circuit board trace
becomes greater than 1Ω, a force/sense amplified con-
figuration should be used to drive this pin (see Figure 2).
Thispreservestheexcellentaccuracy(1LSBINLandDNL)
of the LTC1588/LTC1589/LTC1592.
An Isolated 16-Bit Subsystem Using the LTC1592
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system’s noise floor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practical
for the system resolution desired. Precision voltage refer-
ences, like the LT1236, produce low output noise in the
0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V
or 10V full-scale systems. However, as the circuit band-
widths increase, filtering the output of the reference may
be required to minimize output noise.
ThecircuitinFigure4isacompleteexampleofanoptically
isolated analog output subsystem that supports most of
the legacy ranges that are still common in industrial
environments. This circuit uses only two optoisolators,
the load pulse (CS/LD) being derived from a series of
transitions on the data line (SDI) after the clock (SCK) is
halted high. If a single chip microcontroller with an auto-
mated SPI interface is to be used, the SPI port can transfer
the 24 bits as three bytes. Subsequently, the data output
port pin can be reassigned to general purpose port opera-
tion and exercised to produce a number of transitions to
generate the load pulse. Alternatively, the entire sequence
can be programmed bit by bit with a general purpose port.
Figure 5 shows the timing.
Table 5. Partial List of LTC Precision References Recommended
for Use with the LTC1588/LTC1589/LTC1592 with Relevant
Specifications
The DC/DC converter, Figure 3 based on the LT®3439
ultralow noise transformer driver provides a compact
means of powering this circuit, and allows the output to
deliver output current that is only limited by the LT1468
capabilities. The output capability of the DC/DC converter
itself is 80mA at ±12V and is available as demo board
DC511A. This circuit as shown requires approximately
130mA of the 5V supply (no load). The total surface area
required is less than 2 square inches.
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
REFERENCE
LT1019A-5,
LT1019A-10
±0.05%
±0.05%
±0.075%
±0.05%
5ppm/°C
5ppm/°C
10ppm/°C
10ppm/°C
12µVP-P
LT1236A-5,
LT1236A-10
3µVP-P
LT1460A-5,
LT1460A-10
20µVP-P
12µVP-P
LT1790A-2.5
1588992fa
13
LTC1588/LTC1589/LTC1592
W U U
U
APPLICATIO S I FOR ATIO
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
I
OUT2
200Ω
200Ω
–
+
2
3
6
1000pF
LT1468
1
2
–
+
2
3
ZETEX
BAT54S
6
I
LT1001
OUT2
3
1
2
V
REF
5V
ZETEX*
BAT54S
5
6
3
+
7
1/2 LT1469
*SCHOTTKY BARRIER DIODE
–
C3**
150pF
2
1
16 15
R2
3
4
R1
R
R
REF
R
COM
FB
OFS
C2
R1
R2
15pF
0.1µF
9
15V
8
V
5V
CC
0.1µF
I
I
–
5
OUT1
2
3
1
14
13
12
11
10
12-/14-/16-BIT DAC WITH SPAN ADJUST
LTC1588/LTC1589/LTC1592
V
1/2 LT1469
CLR
CS/LD
SCK
SDI
OUT
6
7
8
OUT2
+
4
AGND
GND
–15V
0.1µF
SDO
1588992 F02
**FOR MULTIPLYING APPLICATIONS C3 = 15pF
Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits
for Driving IOUT2 from AGND with a Force/Sense Amplifier
LT1121-5
5V
2.2µF
3
BYP
LT1761
IN OUT
GND ADJ
C7
E1
IN
5V
D1
V
IN
0.01µF
V
MMBD914
1
5
C1
4.7µF
6.3V
12V
R1
±5%
13
C3
R4
442k
T1
1M
D2
MMBD914
22µF
25V
V
CTX02-16030
2
4
IN
11
5
3
E5
SHDN
R10
10k
SHDN
SYNC
COLA
C5
•
•
+
+
CER
33µF
25V
R5
E7
SYNC
49.9k
TANT
R9
10k
AGND
–12V
C6
D3
MMBD914
LT3439
C4
R6
•
•
33µF
25V
TANT
22µF
25V
CER
49.9k
6
7
14
4
1
4
CT
RT
COLB
RSL
R7
D4
MMBD914
GND ADJ
LT1964
IN OUT
BYP
C2
820pF
442k
5
R2
16.9k
2
R3
15k
GND PGND PGND
10 16
1588992 F03
E6
GND
C8
0.01µF
1
3
C22
2.2nF
1kV
Figure 3. Isolated Power Supplies for the Circuit of Figure 4
1588992fa
14
LTC1588/LTC1589/LTC1592
U
PACKAGE DESCRIPTIO
G Package
16-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
5.90 – 6.50*
(.232 – .256)
1.25 ±0.12
16 15 14 13 12 11 10
9
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
8
1
2
3
4
6
5.00 – 5.60**
(.197 – .221)
2.0
(.079)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
0.05
(.0035 – .010)
(.022 – .037)
0.22 – 0.38
(.009 – .015)
(.002)
G16 SSOP 0802
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1588992fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1588/LTC1589/LTC1592
W U U
U
APPLICATIO S I FOR ATIO
OPTIONAL CIRCUIT FOR 2-WIRE INTERFACE.
FOR A 3-WIRE INTERFACE (SPI), ADD A 3RD
OPTOISOLATOR TO DRIVE CS/LD WITH THE
WAVEFORMS OF FIGURE 1
5V REF
12V
8
10µF
12V
7
74HC161
4
3
4
5
6
2
7
10
9
1
14
13
12
11
ISOLATED
CS/LD
LT1027-5
2
GND
A
B
C
D
QA
QB
QC
QD
0.1µF
+
2
3
–
+
10µF
6
LT1468
4
10µF
CLK
HCPL2300
HCPL2300
ENP
ENT
LD
8
7
5V
5V
–12V
0.1µF
2
3
V
CC
6
5
15
R1
CLR RCO
150pF
7.5k
SCK
5V
2
1
16 15
R2
3
4
TO
R1
R
R
FB
REF
R
COM
OFS
10µF
µCONTROLLER
5V
8
7
15pF
R1
R2
ISOLATED SCK
ISOLATED SDI
2
3
9
V
CC
12V
7
V
6
5
CC
R2
7.5k
0.1µF
I
–
+
OUT1
5
2
3
0.1µF
SDI
AGND
6
14
13
12
11
10
V
OUT
12-/14-/16-BIT DAC WITH SPAN ADJUST
LTC1588/LTC1589/LTC1592
LT1468
CLR
CS/LD
SCK
SDI
10µF
6
7
8
I
OUT2
4
–12V
AGND
GND
SDO
1588992 F04
0.1µF AGND
Figure 4. Optically Isolated 16-Bit SoftSpan System
SCK
SDI
C3
C2
C1
C0
X
D2
D1
D0
CS/LD
1588992 F05
Figure 5. Timing Diagram for the Circuit of Figure 4
RELATED PARTS
PART NUMBER
LTC1591/LTC1597
LTC1595/LTC1596
LTC1599
DESCRIPTION
COMMENTS
On-Chip 4-Quadrant Resistors
Parallel 14-/16-Bit Current Output DACs
Serial 16-Bit Current Output DACs
2-Byte, 16-Bit Current Output DAC
Parallel 16-Bit Voltage Outupt DAC
Octal 16-/14-/12-Bit DACs
Low Glitch, ±1LSB Maximum INL, DNL
On-Chip 4-Quadrant Resistors
LTC1821
Precision 16-Bit Settling in 2µs for 10V Step
Single Supply, µPower in Narrow SSOP16
LTC2600/LTC2610
LTC2620
1588992fa
LT/TP 0503 1K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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